View LE28DW3215AT-80_3372978.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

32 megabit flashbank memory LE28DW3215AT-80 1 sanyo electric co.,ltd.semiconductor company 1-1-1 sakata oizumi gunma japan the flash bank product family was jointly developed by sanyo and s illicon storage technology, inc. (sst), under sst?s technology license. this preliminary secification is subject to change with out noticc. r.0.00 (2002/2/6) no. xxxx -1/17 features: ? single 3.0-volt read and write operations ? separate memory banks by address space ? bank1: 16mbit(1024k x 16) flash ? bank2: 16mbit(1024k x 16) flash ? simultaneous read and write capability ? superior reliability ? endurance: 10,000cycles 100,000cycies(erase verify mode) ? data retention: 10years ? low power consumption ? active current, read: 10ma(typical) ? active current, read & write: 30ma(typical) ? standby current: 5ua(typical) ? auto low power mode current: 5ua(typical) ? fast write operation ? bank erase + program: 15sec(typical) ? block erase + program: 500ms(typical) ? sector erase + program: 45ms(typical) ? read access time ? 80nsec ? latched address and data ? end of write detection ? toggle bit / data# polling ? flash bank: two small erase element sizes ? 2k words per sector or 32k words per block ? erase either element before word program ? cmos i/o compatibility ? packages available ? 48-pin tsop (10mm x 14mm) ? continuous hardware and software data protection (sdp) product description the LE28DW3215AT-80 consists of two memory banks, 2each contains of 1024kx16bits sector mode flash eeprom manufactured with sanyo?s proprietary, high performance flash technology. the LE28DW3215AT-80 writes with a 3.0- volt-only power supply. the LE28DW3215AT-80 is divided into two separate memory banks. each flash bank is typically used for program storage and contains 512sectors of 2k words or 32blocks of 32k words. any bank may be used for executing code while writing data to a different bank. each memory bank is controlled by separate bank selection address (a20) lines. LE28DW3215AT-80 inherently uses less energy during erase, and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the flash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. the auto low power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approximately 1ma/mhz of read cycle time. device operation the LE28DW3215AT-80 operates as two independent 16megabit word program, sector erase flash eeproms. two memory banks are spareted by the address space. the bank1 is assigned as 000000h to 0fffffh, bank2 is assigned as 100000h to 1fffffh. all memory banks share common i/o lines, we#, and oe#. memory bank selection is by bank select address (a20). we# is used with sdp to control the erase and program operation in each memory bank. the LE28DW3215AT-80 provides the added functionality of being able to simultaneously read from one memory bank while erasing, or programming to one other memory bank. once the internally controlled erase or program cycle in a memory bank has commenced, a different memory bank can be accessed for read. also, once we# and ce# are high during the sdp load sequence, a different bank may be accessed to read. LE28DW3215AT-80 which selectes banks (a20) by a address. it can be used as a normal conventinal flash memory when operats erase or program operation to only a bank at non-concurrent operation. the device id cannot be accessed while any bank is writing, erasing, or programming. the auto low power mode automatically puts the LE28DW3215AT-80 in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 10ma to typically 5ua. the auto low power mode reduces the typical i dd active read current to the range of 1ma/mhz of read cycle time. if a concurrent read while write is being performed, the i dd is reduced to typically 40ma. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty.
32 megabit flashbank memory LE28DW3215AT-80 2 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -2/17 read the read operation of the LE28DW3215AT-80 flash banks is controlled by ce# and oe#, a chip enable and output enable both have to be low for the system to obtain data from the outputs. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the timing waveforms for further details (figure3). when the read operation is executed without address change after power switch on, ce# should be changed the level high to low. if the read operation is executed after programming, ce# should be changed the level high to low. write all write operations are initiated by first issuing the software data protect (sdp) entry sequence for bank, block, or sector erase. word program in the selected flash bank. word program and all erase commands have a fixed duration, that will not vary over the life of the device, i.e., are independent of the number of erase/program cycles endured. either flash bank may be read to another flash bank during the internally controlled write cycle. the device is always in the software data protected mode for all write operations write operations are controlled by toggling we# or ce#. the falling edge of we# or ce#, whichever occurs last, latches the address. the rising edge of we# or ce#, whichever occurs first, latches the data and initiates the erase or program cycle. for the purposes of simplification, the following descriptions will assume we# is toggled to initiate an erase or program. toggling the applicable ce# will accomplish the same function. (note, there are separate timing diagrams to illustrate both we# and ce# controlled program or write commands.) word program the word program operation consists of issuing the sdp word program command, initiated by forcing ce# and we# low, and oe# high. the words to be programmed must be in the erased state, prior to programming. the word program command programs the desired addresses word by word. during the word program cycle, the addresses are latched by the falling edge of we#. the data is latched by the rising edge of we#. (see figure4-1 for we# or 4-2 for ce# controlled word program cycle timing waveforms, table3 for the command sequence, and figure15 for a flowchart.) during the erase or program operation, the only valid reads from that bank are data# polling and toggle bit. the other bank may be read. the specified bank, block, or sector erase time is the only time required to erase. there are no preprogramming or other commands or cycles required either internally or externally to erase the bank, block, or sector. erase operations the bank erase is initiated by a specific six-word load sequence (see tables3). a bank erase will typically be less than 70ms. an alternative to the bank erase in the flash bank is the block or sector erase. the block erase will erase an entire block (32k words) in typically 15ms. the sector erase will erase an entire sector (2048 words) in typically 15ms. the sector erase provides a means to alter a single sector using the sector erase and word program modes. the sector erase is initiated by a specific six-word load sequence (see table3). during any sector, block, or bank erase within a bank, any other bank may be read. bank erase the LE28DW3215AT-80 provides a bank erase mode, which allows the user to clear the flash bank to the ?1? state. this is useful when the entire flash must be quickly erased. the software flash bank erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protection operation. after the loading cycle, the device enters into an internally timed cycle. (see table3 for specific codes, figure5-1 for a timing waveform, figure12 for a flowchart.) block erase the LE28DW3215AT-80 provides a block erase mode, which allows the user to clear any block in the flash bank to the ?1? state. the software block erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle. (see table3 for specific codes, figure5-2 for a timing waveform, and figure13 for a flowchart.) during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read. sector erase the LE28DW3215AT-80 provides a sector erase mode, which allows the user to clear any sector in the flash bank to the ?1? state. the software sector erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle. (see table3 for specific codes, figure5-3 for the timing waveform, and figure14 for a flowchart.) during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read.
32 megabit flashbank memory LE28DW3215AT-80 3 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -3/17 write operation status detection the LE28DW3215AT-80 provides two software means to detect the completion of a flash bank program cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq7) and toggle bit (dq6). the end of write detection mode is enabled after the rising edge of we#, which initiates the internal erase or program cycle. the actual completion of the nonvolatile write is a synchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either dq7 or dq6. in order to prevent spurious device rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. there is no provision to abort an erase or program operation, once initiated. for the sanyo flash technology, the associated erase and program times are so fast, relative to system reset times, there is no value in aborting the operation. note, reads can always occur from any bank not performing an erase or program operation. should the system reset, while a block or sector erase or word program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading the bank. since the maximum time the system would have to wait is 25ms(for a block erase), the system ability to read the boot code would not be affected. data# polling (dq7) when the LE28DW3215AT-80 is in the internal flash bank program cycle, any attempt to read dq7 of the last word loaded during the flash bank word load cycle will receive the complement of the true data. once the write cycle is completed, dq7 will show true data. the device is then ready for the next operation. (see figure 6 for the flash bank data polling timing waveforms and figure16 for a flowchart.) toggle bit (dq6) during the flash bank internal write cycle, any consecutive attempts to read dq6 will produce alternating 0?s and 1?s, i. e. toggling between 0 and 1. when the write cycle is completed, the toggling will stop. the device is then ready for the next operation. (see figure 7 for the flash bank toggle bit timing waveforms and figure16 for a flowchart.) hardware data protection noise/glitch protection: a we# pulse of less than 5ns will not initiate a write cycle. vdd power up/down detection: the write operation is inhibited when vdd is less than 1.5voits write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. the LE28DW3215AT-80 provides a protect area by hardware protection. the assigned address is the all area of bank1, which is set up by wp# when low. when this operation is executed, the functions which are sector erase, block erase or word program can not be accepted. when the bank erase operation is executed, all area will be erased except protected area. software data protection (sdp) the LE28DW3215AT-80 provides the jedec approved software data protection scheme as a requirement for initiating a write, erase, or program operation. with this scheme, any write operation requires the inclusion of a series of three word-load operations to precede the word program operation. the three-word load sequence is used to initiate the program cycle, providing optimal protection from inadvertent write operations, e. g., during the system power- up or power-down. the six-word sequence is required to initiate any bank, block, or sector erase operation. the requirements for jedec compliant sdp are in byte format. the le28dw8163t is organized by word; therefore, the contents of dq8 to dq15 are ? don?t care ? during any sdp (3-word or 6-word) command sequence. during the sdp load command sequence, the sdp load cycle is suspended when we# is high. this means a read may occur to any other bank during the sdp load sequence. the bank reserve in sdp load sequence is reserved by the bus cycle of command materialization. if the command sequence is aborted, e. g., an incorrect address is loaded, or incorrect data is loaded, the device will return to the read mode within t rc of execution of the load error.
32 megabit flashbank memory LE28DW3215AT-80 4 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -4/17 concurrent read and write operations the LE28DW3215AT-80 provides the unique benefit of being able to read any bank, while simultaneously erasing, or programming one other bank, this allows data alteration code to be executed from one bank, while altering the data in another bank. the next table lists all valid states. concurrent read/write state table bank1 bank2 read no operation read write write read no operation write write no operation no operation read note: for the purposes of this table, write means to block, sector, or bank erase, or word program as applicable to the appropriate bank. the device will ignore all sdp commands and toggling of we# when an erase or program operation is in progress. note, product identification entry commands use sdp; therefore, this command will also be ignored while an erase or program, operation is in progress. product identification the product identification mode identifies the device manufacturer as sanyo and provides a code to identify each bank. the manufacturer id is the same for each bank; however, each bank has a separate device id. each bank is individually accessed using the applicable bank address and a software command. users may wish to use the device id operation to identify the write algorithm requirements for each bank. (for details, see table 3 for software operation and figure 8 for timing waveforms.) product identification table data maker id 0062h device code(bank1) 25b9h device code(bank2) 25bah device id codes are unique to each bank. should a chip id be required, any of the bank ids may be used as the chip id. while in the read software id mode, no other operation is allowed until after exiting these modes. product identification mode exit in order to return to the standard read mode, the product identification mode must be exited. exit is accomplished by issuing the software id exit command, which returns the device to normal operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e. g., not read correctly. for details, (see table3 for software operation and figures9 for timing waveforms.)
32 megabit flashbank memory LE28DW3215AT-80 5 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -5/17 figure1: pin description: tsop48 (10mm x 14mm) symbol pin name function a20 bank select address to activate the bank1 when low, to activate the bank2 when high. a19-a0 flash bank address to provide flash bank address. a19-a15 flash bank block address to select a flash bank block for erase a19-a10 flash bank sector address to select a flash bank sector for erase dq15-dq0 data input/ output to output data during read cycle and receive input data during write cycle. the output are in tristate when oe# is high or ce# is high. ce# chip enable to activate the flash bank when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write, erase or program operations. vdd power supply to provide 3.0volts supply.(2.7volts to 3.6volts) vss ground nc no connection unconnected pins table1: pin description figure2-1: functionally block diagram tsop-48 typei normal bend (10mm x 14mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a15 a14 a13 a12 a11 a10 a9 a8 we# a19 a20 nc nc ce# nc a18 a17 a7 a6 a5 a4 a3 a2 a1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a16 vss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 nc vdd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 address buffer & data latchs x-decoder y-decoder i/o buffers & data latches control logic a20-a0 ce# oe# we# dq15-dq0 1024k x 16 flash bank2 charge pump & vref. 1024k x 16 flash bank1
32 megabit flashbank memory LE28DW3215AT-80 6 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -6/17 bank1 total 32 block total 512 sector 0f8000h-0fffffh 0f0000h-0f7fffh 0e8000h-0effffh 0e0000h-0e7fffh 0d8000h-0dffffh 0d0000h-0d7fffh 0c8000h-0cffffh 0c0000h-0c7fffh 0b8000h-0bffffh 0b0000h-0b7fffh 0a8000h-0affffh 0a0000h-0a7fffh 098000h-09ffffh 090000h-097fffh 088000h-08ffffh 080000h-087fffh 078000h-07ffffh 070000h-077fffh 068000h-06ffffh 060000h-067fffh 058000h-05ffffh 050000h-057fffh 048000h-04ffffh 040000h-047fffh 038000h-03ffffh 030000h-037fffh 028000h-02ffffh 020000h-027fffh 018000h-01ffffh 010000h-017fffh 008000h-00ffffh 000000h-007fffh 0ff800h-0fffffh 0ff000h-0ff7ffh 0fe800h-0fefffh 0fe000h-0fe7ffh 0fd800h-0fdfffh 0fd000h-0fd7ffh 0fc800h-0fcfffh 0fc000h-0fc7ffh 0fb800h-0fbfffh 0fb000h-0fb7ffh 0fa800h-0fafffh 0fa000h-0fa7ffh 0f9800h-0f9fffh 0f9000h-0f97ffh 0f8800h-0f8fffh 0f8000h-0f87ffh bank2 total 32 block total 512 sector 1f8000h-1fffffh 1f0000h-1f7fffh 1e8000h-1effffh 1e0000h-1e7fffh 1d8000h-1dffffh 1d0000h-1d7fffh 1c8000h-1cffffh 1c0000h-1c7fffh 1b8000h-1bffffh 1b0000h-1b7fffh 1a8000h-1affffh 1a0000h-1a7fffh 198000h-19ffffh 190000h-197fffh 188000h-18ffffh 180000h-187fffh 178000h-17ffffh 170000h-177fffh 168000h-16ffffh 160000h-167fffh 158000h-15ffffh 150000h-157fffh 148000h-14ffffh 140000h-147fffh 138000h-13ffffh 130000h-137fffh 128000h-12ffffh 120000h-127fffh 118000h-11ffffh 110000h-117fffh 108000h-10ffffh 100000h-107fffh 1ff800h-1fffffh 1ff000h-1ff7ffh 1fe800h-1fefffh 1fe000h-1fe7ffh 1fd800h-1fdfffh 1fd000h-1fd7ffh 1fc800h-1fcfffh 1fc000h-1fc7ffh 1fb800h-1fbfffh 1fb000h-1fb7ffh 1fa800h-1fafffh 1fa000h-1fa7ffh 1f9800h-1f9fffh 1f9000h-1f97ffh 1f8800h-1f8fffh 1f8000h-1f87ffh figure2-2: flash sector structure 107800h-107fffh 107000h-1077ffh 106800h-106fffh 106000h-1067ffh 105800h-105fffh 105000h-1057ffh 104800h-104fffh 104000h-1047ffh 103800h-103fffh 103000h-1037ffh 102800h-102fffh 102000h-1027ffh 101800h-101fffh 101000h-1017ffh 100800h-100fffh 100000h-1007ffh 007800h-007fffh 007000h-0077ffh 006800h-006fffh 006000h-0067ffh 005800h-005fffh 005000h-0057ffh 004800h-004fffh 004000h-0047ffh 003800h-003fffh 003000h-0037ffh 002800h-002fffh 002000h-0027ffh 001800h-001fffh 001000h-0017ffh 000800h-000fffh 000000h-0007ffh
32 megabit flashbank memory LE28DW3215AT-80 7 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -7/17 table: 2 operating modes selection array operating mode ce# oe# we# dq a20 a19-a0 read bank1 v il v il v ih d out v il a in bank2 v il v il v ih d out v ih a in block erase bank1 v il v ih v il d in v il see table3 bank2 v il v ih v il d in v ih see table3 sector erase bank1 v il v ih v il d in v il see table3 bank2 v il v ih v il d in v ih see table3 program bank1 v il v ih v il d in v il see table3 bank2 v il v ih v il d in v ih see table3 v ih x x high z x x stand-by write inhibit v ih v il v il xxx bank erase bank1 v il v ih v il d in v il see table3 bank2 v il v ih v il d in v ih see table3 status operating mode ce# oe# we# dq a20 a19-a0 product identification bank1 v il v il v ih d out v il bank2 v il v il v ih d out v ih a 19 -a 1 =v il note3) a 0 =v il or v ih note1: entering an illegal state during an erase, program, or write operation will not affect the operation, i. e., the erase program, or write will continue to normal completion table: 3 software command codes 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle address data address data address data address data address data address data command code note1,4 note5 note1,4 note5 note1,4 note5 note1,4 note5 note1,4 note5 note1,4 note5 software id entry 5555 aa 2aaa 55 5555 +b ax 90 note2 software id exit 5555 aa 2aaa 55 5555 +b ax f0 note3 word program 5555 aa 2aaa 55 5555 a0 word address data in sector erase 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 s ax +b ax 30 block erase 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 l ax +b ax 50 bank erase 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 +b ax 10 notes for software command code: 1.command code address format: a14 - a0 are in hex code. when byte mode, the format is only used by a14-a0. 2.with a19-a0=0; sanyo manufacturer code = 0062h is read with a0=0. sanyo LE28DW3215AT-80 device code 25b9h, 25bah is read with a0=1. 3.the device does not remain in software product id mode if powered down. 4.address a20 to a15 are ? don?t care ? for command sequences. a20 is bank selection address have been reserved in last bus cycle of command sequence. 5.data format dq0 to dq7 are in hex and dq8 to dq15 are ?don?t care?. 6.b ax = bank address: a20, l ax = block address: a19 to a15, s ax = sector address: a19 to a11.
32 megabit flashbank memory LE28DW3215AT-80 8 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -8/17 [ absolute maximum stress ratings ] applied conditions greater then those listed under ?absolute maximum stress ratings ?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those define d in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability. storage temperature : -65c to +150c d.c.voltage on any pin to ground potential : -0.5v to v dd +0.5v transient voltage (<20ns) on any pin to ground potential : -1.0v to v dd +1.0v reset# pin voltage to ground potential : -0.5v to +13.0v package power dissipation capability (ta=25c) : 1.0w [ operating range ] ambient temperature : 0c to +70c v dd : 2.7v to 3.6v [ ac condition of test ] input rise/fall time : 5ns output load (see figures 10 and 11) : c l =30pf [ dc operating characteristics] symbol parameter min max unit test condition i dd power supply current read erase / program read+erase / program 20 40 60 ma ma ma ce#=v il ,we#=v ih , i/o?s open, address input=v il / v ih ,at f=10mhz, v dd =v dd (max) ce#=we#=v il ,oe#=v ih , v dd =v dd (max) ce#=v il ,oe#=we#=v ih , address input=v il / v ih ,at f=10mhz, we#=v ih , v dd =v dd (max) i sb standby current (cmos input) 40 ua ce#=v ihc , v dd =v dd (max) i li i ol input leak current output leak current 10 10 ua ua v in =v ss to v dd , v dd =v dd (max) v out = v ss to v dd , v dd =v dd (max) v il v ilc v ih v ihc input low voltage input low voltage(cmos) input high voltage input high voltage(cmos) v dd *0.8 v dd -0.2 v dd *0.2 0.2 v v v v v ol v oh output low voltage output high voltage v dd -0.2 0.2 v v i ol =100ua , v dd =v dd (min) i oh =-100ua , v dd =v dd (min) [ recommand system power-up timings ] symbol parameter max units t pu -read (1) t pu -write (1) power-up to read operation power-up to write operation 200 200 us us note (1): this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. [ capacitance (ta=25c, f=1mhz,other pins open) ] symbol parameter test condition max c dq (1) c in (1) i/o pin capacitance input capacitance v dq =0v v in =0v 12pf 6pf note (1): this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. [ reliability characteristic ] symbol parameter min spec units n end (1) endurance 10,000 100,000 (2) cycle / sector t dr (1) data retention 10 years note (1): this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. note (2): in case of erase verify mode.
32 megabit flashbank memory LE28DW3215AT-80 9 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -9/17 [ ac characteristic ] read cycle timing parameters symbol parameter min max units t rc read cycle time 80 ns t ce ce# access time 80 ns t aa address access time 80 ns t oe oe# access time 40 ns t clz (1) ce# low to active output 0 ns t olz (1) oe# low to active output 0 ns t chz (1) ce#high to high-z output 30 ns t ohz (1) oe#high to high-z output 30 ns t oh (1) output hold from address change 0 ns write, erase, program cycle, timing parameters symbol parameter min max units t bp word program time 20 us t se sector erase time 25 ms t le block erase time 25 ms t be bank erase time 100 ms t as address setup time 0 ns t ah address hold time 50 ns t ces ce# setup time 0 ns t ceh ce# hold time 0 ns t wes we# setup time 0 ns t weh we# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 0 ns t wp we# puls low width 50 ns t wph we# puls high time 30 ns t ds data setup time 50 ns t dh data hold time 0 ns t vddr (1) vdd rise time 0.1 50 ms t ida id read / exit cycle time 150 ns note (1): this parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
32 megabit flashbank memory LE28DW3215AT-80 10 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -10/17 figure3: read cycle timing diagram figure4-1: we# controlled word program cycle timing diagram t ah address a20-a0 internal program operation starts we# oe# ce# dq15-dq0 t wp t as t ds t dh t ceh t bp word (addr/data) t wph aa sw2 sw1 sw0 t ces 5555 addr 2aaa 5555 55 a0 data data valid t oh t clz high-z t olz t oe t ce t rc t aa v ih address a20-a0 ce# oe# we# dq15-dq0 high-z data valid t ohz t chz
32 megabit flashbank memory LE28DW3215AT-80 11 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -11/17 figure4-2: ce# controlled word program cycle timing diagram figure5-1: bank erase cycle timing diagram t ah address a20-a0 internal program operation starts ce# oe# we# dq15-dq0 t wp t as t ds t dh t weh t bp word ( addr/data ) t wph aa sw2 sw1 sw0 t wes 5555 addr 2aaa 5555 55 a0 data t ah address a20-a0 six-byte code for bank erase we# oe# ce# dq15-dq0 t wp t ds t dh t be t wph aa sw1 sw0 t as 5555 55 2aaa 5555 5555 2aaa sw2 80 sw3 aa sw4 55 sw5 10 5555+ b ax
32 megabit flashbank memory LE28DW3215AT-80 12 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -12/17 figure5-2: block erase cycle timing diagram figure5-3: sector erase cycle timing diagram t ah address a20-a0 six-byte code for block erase we# oe# ce# dq15-dq0 t wp t ds t dh t le t wph aa sw1 sw0 t as 5555 55 2aaa 5555 5555 2aaa l ax + b ax sw2 80 sw3 aa sw4 55 sw5 50 t ah address a20-a0 six-byte code for sector erase we# oe# ce# dq15-dq0 t wp t ds t dh t se t wph aa sw1 sw0 t as 5555 55 2aaa 5555 5555 2aaa s ax +b ax sw2 80 sw3 aa sw4 55 sw5 30
32 megabit flashbank memory LE28DW3215AT-80 13 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -13/17 figure6: data# polling timing diagram figure7: toggle bit timing diagram address a20-a0 we# oe# ce# dq7 t ce t oeh t oe t oes data# data# data# data# address a20-a0 we# oe# ce# dq6 t oeh t oe t oes t ce two read cycle with same outputs
32 megabit flashbank memory LE28DW3215AT-80 14 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -14/17 figure8: software id entry and read figure9: software id exit address a20-a0 three-byte sequence for software id exit we# oe# ce# dq15-dq0 t wp t wph aa 5555 55 2aaa 5555+ b ax f0 t ida sw0 sw1 sw2 address a20-a0 three-byte sequence for software id entr y we# oe# ce# dq15-dq0 t wp t wph aa 5555 55 2aaa 5555+b ax 90 t ida 0000+b ax 0062 25b9/25ba sw0 sw1 sw2 t aa 0001+b ax
32 megabit flashbank memory LE28DW3215AT-80 15 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -15/17 ac test inputs are driven at viht (vdd*0.9) for a logic ?1? and vilt (vdd*0.1) for a logic ?0? measurement reference points for inputs and outputs are at vht (vdd*0.7) and vlt (vdd*0.3) input rise and fall times (10% to 90%) are<10ns. figure10: ac i/o reference waveforms figure11: a test load example v ih t v ilt in p u t reference points v ht v lt v ht v lt output to dut to tester c l v dd r l low r l high
32 megabit flashbank memory LE28DW3215AT-80 16 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -16/17 figure12: bank erase flowchart figure13: block erase flowchart figure14: sector erase flowchart figure15: word program flowchart bank erase start software data protect bank erase command wait for end of erase (t be , data# polling,or toggle bit) bank erase complete block erase start software data protect block erase command wait for end of erase (t le , data# polling, or toggle bit) block erase complete set block address sector erase start software data protect sector erase command wait for end of erase (t se , data# polling,or toggle bit) set sector address set sector address sector erase complete word program start software data protect word program command set word address load word data wait for end of program (t bp , data# polling or toggle bit) word program complete
32 megabit flashbank memory LE28DW3215AT-80 17 sanyo electric co., ltd. semiconductor company 1-1-1 sakata oizumi gunma japan r.0.00 (2002/2/6) no. xxxx -17/17 figure16: end of erase or program wait options flowchart no yes internal timer erase or program operation initiated wait for t bp , t be , t le , t se erase of program completed toggle bit erase or program operation initiated read a word from selected bank, block, sector, or word read the same word again is dq6 the same? erase or program completed data# polling erase or program operation initiated read dq7 of the last address set ( or any address with in selected bank, block, sector, for erase ) is dq7 same as bit loaded? erase or program completed no yes

▲Up To Search▲

Price & Availability of LE28DW3215AT-80

	To Download LE28DW3215AT-80 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .